emmc.h (4291B)
1 #pragma once 2 3 // Raspberry Pi EMMC driver adapted from Low Level Devel: 4 // https://github.com/rockytriton/LLD 5 6 #include <stdint.h> 7 #include <stdbool.h> 8 9 typedef uint8_t u8; 10 typedef uint16_t u16; 11 typedef uint32_t u32; 12 typedef uint64_t u64; 13 14 typedef volatile u32 reg32; 15 16 #define EMMC_DEBUG 0 17 18 #define BSWAP32(x) (((x << 24) & 0xff000000 ) | \ 19 ((x << 8) & 0x00ff0000 ) | \ 20 ((x >> 8) & 0x0000ff00 ) | \ 21 ((x >> 24) & 0x000000ff )) 22 23 typedef struct { 24 u8 resp_a : 1; 25 u8 block_count : 1; 26 u8 auto_command : 2; 27 u8 direction : 1; 28 u8 multiblock : 1; 29 u16 resp_b : 10; 30 u8 response_type : 2; 31 u8 res0 : 1; 32 u8 crc_enable : 1; 33 u8 idx_enable : 1; 34 u8 is_data : 1; 35 u8 type : 2; 36 u8 index : 6; 37 u8 res1 : 2; 38 } emmc_cmd; 39 40 #define RES_CMD {1, 1, 3, 1, 1, 0xF, 3, 1, 1, 1, 1, 3, 0xF, 3} 41 42 typedef enum { 43 RTNone, 44 RT136, 45 RT48, 46 RT48Busy 47 } cmd_resp_type; 48 49 typedef enum { 50 CTGoIdle = 0, 51 CTSendCide = 2, 52 CTSendRelativeAddr = 3, 53 CTIOSetOpCond = 5, 54 CTSelectCard = 7, 55 CTSendIfCond = 8, 56 CTSetBlockLen = 16, 57 CTReadBlock = 17, 58 CTReadMultiple = 18, 59 CTWriteBlock = 24, 60 CTWriteMultiple = 25, 61 CTOcrCheck = 41, 62 CTSendSCR = 51, 63 CTApp = 55 64 } cmd_type; 65 66 typedef struct { 67 u32 scr[2]; 68 u32 bus_widths; 69 u32 version; 70 } scr_register; 71 72 typedef enum { 73 SDECommandTimeout, 74 SDECommandCrc, 75 SDECommandEndBit, 76 SDECommandIndex, 77 SDEDataTimeout, 78 SDEDataCrc, 79 SDEDataEndBit, 80 SDECurrentLimit, 81 SDEAutoCmd12, 82 SDEADma, 83 SDETuning, 84 SDERsvd 85 } sd_error; 86 87 typedef struct { 88 bool last_success; 89 u32 transfer_blocks; 90 emmc_cmd last_command; 91 reg32 last_command_value; 92 u32 block_size; 93 u32 last_response[4]; 94 bool sdhc; 95 u16 ocr; 96 u32 rca; 97 u64 offset; 98 void *buffer; 99 u32 base_clock; 100 u32 last_error; 101 u32 last_interrupt; 102 scr_register scr; 103 } emmc_device; 104 105 typedef struct { 106 reg32 arg2; 107 reg32 block_size_count; 108 reg32 arg1; 109 reg32 cmd_xfer_mode; 110 reg32 response[4]; 111 reg32 data; 112 reg32 status; 113 reg32 control[2]; 114 reg32 int_flags; 115 reg32 int_mask; 116 reg32 int_enable; 117 reg32 control2; 118 reg32 cap1; 119 reg32 cap2; 120 reg32 res0[2]; 121 reg32 force_int; 122 reg32 res1[7]; 123 reg32 boot_timeout; 124 reg32 debug_config; 125 reg32 res2[2]; 126 reg32 ext_fifo_config; 127 reg32 ext_fifo_enable; 128 reg32 tune_step; 129 reg32 tune_SDR; 130 reg32 tune_DDR; 131 reg32 res3[23]; 132 reg32 spi_int_support; 133 reg32 res4[2]; 134 reg32 slot_int_status; 135 } emmc_regs; 136 137 #define TO_REG(p) *((reg32 *)p) 138 139 // SD Clock Frequencies (in Hz) 140 #define SD_CLOCK_ID 400000 141 #define SD_CLOCK_NORMAL 25000000 142 #define SD_CLOCK_HIGH 50000000 143 #define SD_CLOCK_100 100000000 144 #define SD_CLOCK_208 208000000 145 #define SD_COMMAND_COMPLETE 1 146 #define SD_TRANSFER_COMPLETE (1 << 1) 147 #define SD_BLOCK_GAP_EVENT (1 << 2) 148 #define SD_DMA_INTERRUPT (1 << 3) 149 #define SD_BUFFER_WRITE_READY (1 << 4) 150 #define SD_BUFFER_READ_READY (1 << 5) 151 #define SD_CARD_INSERTION (1 << 6) 152 #define SD_CARD_REMOVAL (1 << 7) 153 #define SD_CARD_INTERRUPT (1 << 8) 154 155 #define EMMC_BASE 0x20300000 156 157 #define EMMC ((emmc_regs *)EMMC_BASE) 158 159 #define EMMC_CTRL1_RESET_DATA (1 << 26) 160 #define EMMC_CTRL1_RESET_CMD (1 << 25) 161 #define EMMC_CTRL1_RESET_HOST (1 << 24) 162 #define EMMC_CTRL1_RESET_ALL (EMMC_CTRL1_RESET_DATA | EMMC_CTRL1_RESET_CMD | EMMC_CTRL1_RESET_HOST) 163 164 #define EMMC_CTRL1_CLK_GENSEL (1 << 5) 165 #define EMMC_CTRL1_CLK_ENABLE (1 << 2) 166 #define EMMC_CTRL1_CLK_STABLE (1 << 1) 167 #define EMMC_CTRL1_CLK_INT_EN (1 << 0) 168 169 #define EMMC_CTRL0_ALT_BOOT_EN (1 << 22) 170 #define EMMC_CTRL0_BOOT_EN (1 << 21) 171 #define EMMC_CTRL0_SPI_MODE (1 << 20) 172 173 #define EMMC_STATUS_DAT_INHIBIT (1 << 1) 174 #define EMMC_STATUS_CMD_INHIBIT (1 << 0) 175 176 bool emmc_init(); 177 int emmc_read(u32 sector, u8* buffer, u32 size); 178 int emmc_write(u32 sector, u8* buffer, u32 size); 179 180 // bzt compat layer. 181 #define SD_OK 1 182 static inline int sd_init(void) { 183 return emmc_init(); 184 } 185 static inline int 186 sd_readblock(uint32_t sec, void *data, unsigned nsec) { 187 return emmc_read(sec, data, nsec*512); 188 } 189 static inline int 190 sd_writeblock(const void *data, uint32_t sec, unsigned nsec) { 191 return emmc_write(sec, (void*)data, nsec*512); 192 }