sylveos

mini-uart.zig (13617B)

---

 const std = @import("std");
 
 const StackRingBuffer = @import("shared").StackRingBuffer;
 
 const interrupts = @import("../interrupts.zig");
 const mem = @import("../mem.zig");
 
 const clock = @import("./clock.zig");
 const gpio = @import("./gpio.zig");
 
 pub const Error = error{ AlreadyInitialized, NotInitialized, InvalidReadLimit, Timeout } || gpio.Error;
 
 // Page 8: Auxiliary peripherals Register Map
 const BASE_ADDRESS: usize = mem.BASE_ADDRESS + 0x0021_5000;
 const AUX_ENABLES: usize = BASE_ADDRESS + 0x0004;
 const AUX_MU_IO_REG: usize = BASE_ADDRESS + 0x0040;
 const AUX_MU_IER_REG: usize = BASE_ADDRESS + 0x0044;
 const AUX_MU_IIR_REG: usize = BASE_ADDRESS + 0x0048;
 const AUX_MU_LCR_REG: usize = BASE_ADDRESS + 0x004C;
 const AUX_MU_MCR_REG: usize = BASE_ADDRESS + 0x0050;
 const AUX_MU_LSR_REG: usize = BASE_ADDRESS + 0x0054;
 const AUX_MU_MSR_REG: usize = BASE_ADDRESS + 0x0058;
 const AUX_MU_SCRATCH: usize = BASE_ADDRESS + 0x005C;
 const AUX_MU_CNTL_REG: usize = BASE_ADDRESS + 0x0060;
 const AUX_MU_STAT_REG: usize = BASE_ADDRESS + 0x0064;
 const AUX_MU_BAUD_REG: usize = BASE_ADDRESS + 0x0068;
 
 const CLOCK_FREQ = 250_000_000;
 
 const TxPin = enum(u8) {
     Gpio14 = 14,
     Gpio32 = 32,
     Gpio36 = 36,
 };
 const RxPin = enum(u8) {
     Gpio15 = 15,
     Gpio33 = 33,
     Gpio37 = 37,
 };
 
 var initialized = false;
 var rx_interrupts_enabled = false;
 var tx_interrupts_enabled = false;
 var use_tx_interrupts = false;
 
 pub fn initialize(baud: u32, tx_pin: TxPin, rx_pin: RxPin) Error!void {
     if (initialized) return Error.AlreadyInitialized;
 
     // Set GPIO pins first (as specified by manual)
     // Page 102 specifies which alt mode
     const tx_fn: gpio.FunctionSelect = switch (tx_pin) {
         .Gpio14 => .alt_fn_5,
         .Gpio32 => .alt_fn_3,
         .Gpio36 => .alt_fn_2,
     };
     const rx_fn: gpio.FunctionSelect = switch (rx_pin) {
         .Gpio15 => .alt_fn_5,
         .Gpio33 => .alt_fn_3,
         .Gpio37 => .alt_fn_2,
     };
 
     // The error case is technically unreachable due to hardcoding gpio pin values
     // But at the same time this function body may change with time so it's important
     // to keep the Error
     try gpio.fn_sel(@intFromEnum(tx_pin), tx_fn);
     try gpio.fn_sel(@intFromEnum(rx_pin), rx_fn);
 
     try gpio.set_pull(@intFromEnum(tx_pin), .Off);
     try gpio.set_pull(@intFromEnum(rx_pin), .Off);
 
     // AUX_ENABLES needs bit 0 set to 1
     // Page 9: AUXENB Register
     mem.put_u32(@ptrFromInt(AUX_ENABLES), 1);
 
     // Disable interrupts
     // Page 12: AUX_MU_IER_REG Register
     // When bit 0/1 is 0, interrupts are disabled
     mem.put_u32(@ptrFromInt(AUX_MU_IER_REG), 0);
 
     // Disable RX/TX during configuration
     // Page 17: AUX_MU_CNTL_REG Register
     // When bit 0/1 is 0, UART receiver/transmitter is disabled
     mem.put_u32(@ptrFromInt(AUX_MU_CNTL_REG), 0);
 
     // Set data size to 8 bits
     // Page 14: AUX_MU_LCR_REG Register
     // When bit 0 is 1, UART is in 8-bit mode, else 7-bit
     // Errata: "bit 1 must be set for 8 bit mode"
     mem.put_u32(@ptrFromInt(AUX_MU_LCR_REG), 0b11);
 
     // Put RTS high (indicate request to send)
     // Page 14: AUX_MU_MCR_REG Register
     // When bit 1 is 0, RTS line is high, else low
     mem.put_u32(@ptrFromInt(AUX_MU_MCR_REG), 0);
 
     // Clear FIFO
     // Page 13: AUX_MU_IER_REG Register
     // When bit 1/2 is 1, receive/transmit will be cleared
     mem.put_u32(@ptrFromInt(AUX_MU_IIR_REG), 0b110);
 
     // Set baud rate
     // Page 11: 2.2.1 Mini UART Implementation Details
     // The baudrate formula is given as (system_clock_freq)/(8 * (baudrate_reg + 1))
     mem.put_u32(@ptrFromInt(AUX_MU_BAUD_REG), CLOCK_FREQ / (8 * baud) - 1);
 
     // Enable RX/TX again
     // Page 17: AUX_MU_CNTL_REG Register
     // When bit 0/1 is 1, UART receiver/transmitter is enabled
     mem.put_u32(@ptrFromInt(AUX_MU_CNTL_REG), 0b11);
 
     mem.barrier(.Write);
 
     initialized = true;
 }
 
 pub fn set_rx_interrupts(state: bool) Error!void {
     if (state) {
         try enable_rx_interrupts();
     } else {
         try disable_rx_interrupts();
     }
 }
 
 fn interrupt_state(tx: bool, rx: bool) void { // Enable RX/TX Interrupts
     // Page 12: AUX_MU_IIR_REG Register
     // Bit 0 - RX Interrupt
     // Bit 1 - TX Interrupt
     // Errata: "Bits 1:0 are swapped. bit 0 is receive
     // interrupt and bit 1 is transmit."
     // Errata: "Bits 3:2 are marked as don't care, but
     // are actually required in order to receive interrupts."
     if (tx and rx) {
         mem.put_u32_barrier(@ptrFromInt(AUX_MU_IER_REG), 0b1111);
     } else if (tx and !rx) {
         mem.put_u32_barrier(@ptrFromInt(AUX_MU_IER_REG), 0b1110);
     } else if (!tx and rx) {
         mem.put_u32_barrier(@ptrFromInt(AUX_MU_IER_REG), 0b0101);
     } else if (!tx and !rx) {
         mem.put_u32_barrier(@ptrFromInt(AUX_MU_IER_REG), 0b0000);
     }
 }
 
 // Separate function to allow TX used during early boot
 fn enable_rx_interrupts() Error!void {
     if (!initialized) return Error.NotInitialized;
     if (rx_interrupts_enabled) return Error.AlreadyInitialized;
 
     mem.barrier(.Write);
 
     interrupts.set_exception_handler(.IRQ, uart_handler);
     interrupts.enable_peripheral_interrupt(.AuxInterrupt);
 
     interrupt_state(tx_interrupts_enabled, true);
 
     rx_interrupts_enabled = true;
 }
 
 fn disable_rx_interrupts() Error!void {
     if (!initialized) return Error.NotInitialized;
     if (!rx_interrupts_enabled) return Error.NotInitialized;
 
     mem.barrier(.Write);
 
     interrupt_state(tx_interrupts_enabled, false);
 
     rx_interrupts_enabled = false;
 }
 
 pub fn set_tx_interrupts(state: bool) void {
     use_tx_interrupts = state;
 
     if (state) {
         interrupts.set_exception_handler(.IRQ, uart_handler);
         interrupts.enable_peripheral_interrupt(.AuxInterrupt);
     } else {
         drain_write_queue();
     }
 }
 
 fn enable_tx_interrupt() !void {
     if (!initialized) return Error.NotInitialized;
 
     interrupt_state(true, rx_interrupts_enabled);
 
     tx_interrupts_enabled = true;
 }
 
 fn disable_tx_interrupt() !void {
     if (!initialized) return Error.NotInitialized;
 
     interrupt_state(false, rx_interrupts_enabled);
 
     tx_interrupts_enabled = false;
 }
 
 fn drain_write_queue() void {
     const cs = mem.enter_critical_section();
     defer cs.exit();
 
     while (tx_list.pop()) |b| {
         write_byte_sync(b);
     }
 }
 
 var tx_list: StackRingBuffer(u8, 128) = .init();
 
 var rx_list: StackRingBuffer(u8, 128) = .init();
 var rx_writer: ?*std.Io.Writer = null;
 var rx_writer_written: usize = 0;
 
 pub fn switch_rx_writer(rx_w: ?*std.Io.Writer) !void {
     const cs = mem.enter_critical_section();
     defer cs.exit();
 
     rx_writer_written = 0;
 
     if (rx_w) |w| {
         // Copy buffer into new writer
         while (rx_list.pop()) |b| {
             try w.writeByte(b);
             rx_writer_written += 1;
         }
     }
 
     rx_writer = rx_w;
 }
 
 pub fn get_rx_written() usize {
     const cs = mem.enter_critical_section();
     defer cs.exit();
 
     return rx_writer_written;
 }
 
 noinline fn uart_handler(_: interrupts.Registers, _: interrupts.ExceptionVector) void {
     mem.barrier(.Write);
     defer mem.barrier(.Write);
 
     if (!initialized) return;
     if (!interrupts.pending_peripheral_interrupt(.AuxInterrupt)) return;
 
     while (true) {
         const IIR = mem.get_u32(@ptrFromInt(AUX_MU_IIR_REG));
 
         // UART interrupt pending
         if ((IIR & 0b1) == 1) return;
 
         switch (IIR & 0b110) {
             // RX has byte
             0b100 => {
                 const b = read_byte_raw();
                 if (rx_writer) |w| {
                     rx_writer_written += 1;
                     w.writeByte(b) catch {};
                 } else {
                     rx_list.push(b) catch {};
                 }
             },
             // TX has space
             0b010 => {
                 if (tx_list.pop()) |byte| {
                     mem.put_u32_barrier(@ptrFromInt(AUX_MU_IO_REG), @as(u32, byte) & 0xFF);
                 } else {
                     disable_tx_interrupt() catch {};
                     return;
                 }
             },
             // Unknown
             else => break,
         }
     }
 }
 
 pub fn is_initialized() bool {
     return initialized;
 }
 
 const Status = packed struct(u32) {
     rx_has_symbol: bool,
     tx_has_space: bool,
     rx_is_idle: bool,
     tx_is_idle: bool,
     rx_overrun: bool,
     tx_full: bool,
     rts_status: bool,
     ctx_status: bool,
     tx_is_empty: bool,
     tx_done: bool,
     _reserved_10_15: u6,
     rx_fill_level: u4,
     _reserved_20_23: u4,
     tx_fill_level: u4,
     _reserved_28_31: u4,
 };
 
 pub fn status() Status {
     return @bitCast(mem.get_u32_barrier(@ptrFromInt(AUX_MU_STAT_REG)));
 }
 
 pub fn read_queue_length() usize {
     const cs = mem.enter_critical_section();
     defer cs.exit();
 
     return rx_list.length();
 }
 
 pub fn write_queue_length() usize {
     // Queuing disabled
     const cs = mem.enter_critical_section();
     defer cs.exit();
 
     return tx_list.length();
 }
 
 pub fn can_read() bool {
     // Check if FIFO has data
     // Page 15: AUX_MU_LSR_REG Register
     // Bit 1 is set when FIFO holds at least 1 byte
     return read_queue_length() > 0 or can_read_raw();
 }
 
 // // TODO; is this necessary
 inline fn can_read_raw() bool {
     return (mem.get_u32_barrier(@ptrFromInt(AUX_MU_LSR_REG)) & 0x01) == 1;
 }
 
 pub fn read_byte_sync_timeout(timeout: ?u64) !u8 {
     var wait_until: u64 = std.math.maxInt(u64);
 
     if (timeout) |t| {
         wait_until = clock.current_count() + t;
     }
 
     while (true) {
         if (clock.current_count() > wait_until) {
             return Error.Timeout;
         }
 
         if (!can_read()) continue;
 
         if (read_queue_length() > 0) {
             return read_byte_async().?;
         } else {
             return read_byte_raw();
         }
 
         return;
     }
 }
 
 pub fn read_byte_sync() u8 {
     return read_byte_sync_timeout(null) catch unreachable;
 }
 
 pub fn read_byte_async() ?u8 {
     const cs = mem.enter_critical_section();
     defer cs.exit();
 
     return rx_list.pop();
 }
 
 inline fn read_byte_raw() u8 {
     return @truncate(mem.get_u32_barrier(@ptrFromInt(AUX_MU_IO_REG)));
 }
 
 pub fn can_write() bool {
     // Check if FIFO can accept data
     // Page 15: AUX_MU_LSR_REG Register
     // Bit 5 is set when FIFO can accept at least 1 byte
     return (mem.get_u32_barrier(@ptrFromInt(AUX_MU_LSR_REG)) & 0x20) != 0;
 }
 
 // pub fn write_queued() usize {
 //     return tx_list.items.len;
 // }
 
 pub fn write_byte_async(byte: u8) !void {
     const cs = mem.enter_critical_section();
     defer cs.exit();
 
     try tx_list.push(byte);
 
     // Let TX start draining
     enable_tx_interrupt() catch {};
 }
 
 pub fn write_byte_sync_timeout(byte: u8, timeout: ?u64) !void {
     var wait_until: u64 = std.math.maxInt(u64);
 
     if (timeout) |t| {
         wait_until = clock.current_count() + t;
     }
 
     while (true) {
         if (clock.current_count() > wait_until) {
             return Error.Timeout;
         }
 
         if (!can_write()) continue;
 
         write_byte_raw(byte);
 
         return;
     }
 }
 
 pub fn write_byte_sync(byte: u8) void {
     write_byte_sync_timeout(byte, null) catch {};
 }
 
 inline fn write_byte_raw(byte: u8) void {
     mem.put_u32_barrier(@ptrFromInt(AUX_MU_IO_REG), @as(u32, byte) & 0xFF);
 }
 
 pub fn write_byte(byte: u8) void {
     if (use_tx_interrupts) {
         write_byte_async(byte) catch {
             write_byte_sync(byte);
         };
     } else {
         write_byte_sync(byte);
     }
 }
 
 pub fn write_slice(bytes: []const u8) void {
     for (bytes) |b| {
         write_byte(b);
     }
 }
 
 pub fn write_slice_sync(bytes: []const u8) void {
     for (bytes) |b| {
         write_byte_sync(b);
     }
 }
 
 pub fn flush() void {
     // Loop until there's nothing left in TX queue
     while (true) {
         const s = status();
 
         if (tx_interrupts_enabled == false and write_queue_length() > 0) {
             drain_write_queue();
         }
 
         if (s.tx_is_empty and s.tx_is_idle and write_queue_length() == 0) break;
     }
 }
 
 fn writer_drain(io_w: *std.Io.Writer, data: []const []const u8, splat: usize) !usize {
     if (!initialized) return std.Io.Writer.Error.WriteFailed;
 
     // We don't care about getting the "parent"
     _ = io_w;
     _ = splat;
 
     write_slice(data[0]);
 
     return data[0].len;
 }
 
 fn writer_flush(io_w: *std.Io.Writer) !void {
     if (!initialized) return std.Io.Writer.Error.WriteFailed;
 
     // We don't care about getting the "parent"
     _ = io_w;
 
     flush();
 }
 
 pub fn print(comptime fmt: []const u8, args: anytype) void {
     writer.print(fmt, args) catch {};
 }
 
 const writer_vtable: std.Io.Writer.VTable = .{ .drain = writer_drain, .flush = writer_flush };
 pub var writer = std.Io.Writer{ .buffer = undefined, .vtable = &writer_vtable };
 
 fn stream(io_r: *std.Io.Reader, io_w: *std.Io.Writer, limit: std.Io.Limit) !usize {
     // We don't care about getting the "parent"
     _ = io_r;
 
     if (limit.toInt()) |max| {
         if (max > rx_list.items.len and rx_interrupts_enabled) {
             // Use direct writes when there's a large buffer
             try switch_rx_writer(io_w);
 
             while (get_rx_written() < max) {}
 
             try switch_rx_writer(null);
         } else {
             // Small buffers should just read blocking
             for (0..max) |_| {
                 try io_w.writeByte(read_byte_sync());
             }
         }
 
         return max;
     } else {
         return std.Io.Reader.StreamError.ReadFailed;
     }
 }
 
 const reader_vtable: std.Io.Reader.VTable = .{ .stream = stream };
 pub var reader = std.Io.Reader{ .buffer = undefined, .seek = 0, .end = 0, .vtable = &reader_vtable };