sylveos

spi.zig (6028B)

---

 const std = @import("std");
 
 const mem = @import("../mem.zig");
 const gpio = @import("./gpio.zig");
 const register = @import("../register.zig");
 
 const BASE_ADDRESS: usize = mem.BASE_ADDRESS + 0x0020_4000;
 const CS: register.Register(MasterControlStatus, .ReadModifyWrite) = .init(BASE_ADDRESS + 0x00);
 const FIFO: register.Register(u32, .ReadModifyWrite) = .init(BASE_ADDRESS + 0x04);
 const CLK: register.Register(Clk, .ReadModifyWrite) = .init(BASE_ADDRESS + 0x08);
 const DATA_LENGTH: register.Register(DataLength, .ReadModifyWrite) = .init(BASE_ADDRESS + 0x0C);
 const LTOH: register.Register(Ltoh, .ReadModifyWrite) = .init(BASE_ADDRESS + 0x10);
 const DC: register.Register(Dc, .ReadModifyWrite) = .init(BASE_ADDRESS + 0x14);
 
 const MasterControlStatus = packed struct(u32) {
     pub const ChipSelect = enum(u2) {
         @"0" = 0b00,
         @"1" = 0b01,
         @"2" = 0b10,
     };
 
     pub const ClockPhase = enum(u1) {
         Middle = 0,
         Beginning = 1,
     };
 
     pub const ClockPolarity = enum(u1) {
         Low = 0,
         High = 1,
     };
 
     pub const FiFoClear = packed struct(u2) {
         clear_tx: bool,
         clear_rx: bool,
     };
 
     pub const ChipSelectPolarity = enum(u1) {
         ActiveLow = 0,
         ActiveHigh = 1,
     };
 
     pub const Ren = enum(u1) {
         Write = 0,
         Read = 1,
     };
 
     pub const Len = enum(u1) {
         SPIMaster = 0,
         LoSSIMaster = 1,
     };
 
     chip_select: ChipSelect = .@"0",
     clock_phase: ClockPhase = .Middle,
     clock_polarity: ClockPolarity = .Low,
     clear_fifo: FiFoClear = .{ .clear_tx = false, .clear_rx = false },
     // elinux bcm2835 errata:
     // "There is a CSPOL bit described here, wereas there are also CSPOL[0,1,2]
     // described on page 153. How do these combine???"
     // Linux sets both this and chip_select_N together
     chip_select_polarity: ChipSelectPolarity = .ActiveLow,
     transfer_active: bool = false,
     dma_enable: bool = false,
     interrupt_on_done: bool = false,
     interrupt_on_rx: bool = false,
     automatically_deassert_chip_select: bool = false,
     ren: Ren = .Write,
     len_lossi_enable: Len = .SPIMaster,
     _unused_14: u1 = 0,
     _unused_15: u1 = 0,
     done: bool = false,
     rxd_contains_data: bool = false,
     txd_has_space: bool = true,
     rxr_is_full: bool = false,
     rxf_is_full: bool = false,
     chip_select_0: ChipSelectPolarity = .ActiveLow,
     chip_select_1: ChipSelectPolarity = .ActiveLow,
     chip_select_2: ChipSelectPolarity = .ActiveLow,
     dma_enable_lossi: bool = false,
     lossi_write_u32: bool = false,
     _reserved_31_26: u6 = 0,
 };
 
 const Clk = packed struct(u32) {
     clock_divider: u16 = 0,
     _reserved_31_16: u16 = 0,
 };
 
 const DataLength = packed struct(u32) {
     length: u16,
     _reserved_31_16: u16,
 };
 
 const Ltoh = packed struct(u32) {
     toh: u4,
     _reserved_31_4: u28,
 };
 
 const Dc = packed struct(u32) {
     dma_write_request_threshold: u8,
     dma_write_panic_threshold: u8,
     dma_read_request_threshold: u8,
     dma_read_panic_threshold: u8,
 };
 
 // Polled:
 // 1. Set CS(MasterControlStatus), CPOL(chip_select_polarity), CPHA(clock_phase)
 //    as required and set TA(transfer_active) = 1
 // 2. Poll TXD(txd_has_space) writing bytes to SPI_FIFO(FiFo), RXD(rxd_contains_data)
 //    reading bytes from SPI_FIFO(FiFo) until all data is written
 // 3. Poll DONE(transfer_progress) until it goes to 1
 // 4. Set TA(transfer_active) = 0
 pub const SpiConfig = struct {
     chip_select: MasterControlStatus.ChipSelect,
     chip_select_polarity: MasterControlStatus.ChipSelectPolarity = .ActiveLow,
     clock_polarity: MasterControlStatus.ClockPolarity = .Low,
     clock_phase: MasterControlStatus.ClockPhase = .Middle,
     pins: enum(u8) {
         Lower = 7,
         Upper = 35,
     },
 };
 
 pub fn init(config: *const SpiConfig, clock: u16) void {
     const ce1 = @intFromEnum(config.pins);
     gpio.fn_sel(ce1, .alt_fn_0) catch {};
     gpio.set_pull(ce1, .Off) catch {};
 
     gpio.fn_sel(ce1 + 1, .alt_fn_0) catch {};
     gpio.set_pull(ce1 + 1, .Off) catch {};
 
     gpio.fn_sel(ce1 + 2, .alt_fn_0) catch {};
     gpio.set_pull(ce1 + 2, .Off) catch {};
 
     gpio.fn_sel(ce1 + 3, .alt_fn_0) catch {};
     gpio.set_pull(ce1 + 3, .Off) catch {};
 
     gpio.fn_sel(ce1 + 4, .alt_fn_0) catch {};
     gpio.set_pull(ce1 + 4, .Off) catch {};
 
     // Set Clock
     CLK.set(.{
         .clock_divider = clock,
     });
 }
 
 pub fn get_base_config(config: *const SpiConfig) MasterControlStatus {
     var cs: MasterControlStatus = .{};
 
     cs.chip_select = config.chip_select;
     cs.chip_select_polarity = config.chip_select_polarity;
     cs.clock_polarity = config.clock_polarity;
     cs.clock_phase = config.clock_phase;
 
     switch (config.chip_select) {
         .@"0" => cs.chip_select_0 = config.chip_select_polarity,
         .@"1" => cs.chip_select_1 = config.chip_select_polarity,
         .@"2" => cs.chip_select_2 = config.chip_select_polarity,
     }
 
     return cs;
 }
 
 fn clear_fifo(config: *const SpiConfig) void {
     var base = get_base_config(config);
     base.clear_fifo = .{ .clear_rx = true, .clear_tx = true };
     CS.set(base);
 }
 
 fn start_transfer(config: *const SpiConfig) void {
     CS.set(get_base_config(config));
     clear_fifo(config);
     var base = get_base_config(config);
     base.transfer_active = true;
     CS.set(base);
 }
 
 fn end_transfer(config: *const SpiConfig) void {
     var base = get_base_config(config);
     base.transfer_active = false;
     CS.set(base);
 }
 
 pub fn transfer(config: *const SpiConfig, src: []const u8, dst: []u8) void {
     start_transfer(config);
 
     for (0..@max(src.len, dst.len)) |i| {
         while (!CS.get().txd_has_space) {}
 
         if (i < src.len) {
             FIFO.set(@as(u32, src[i]));
         } else {
             FIFO.set(0x00);
         }
 
         while (!CS.get().rxd_contains_data) {}
 
         if (i < dst.len) {
             dst[i] = @truncate(FIFO.get());
         } else {
             _ = FIFO.get();
         }
     }
 
     while (!CS.get().done) {}
 
     end_transfer(config);
 }