sylveos

mmu.zig (17789B)

---

 const system = @import("./system.zig");
 const mem = @import("./mem.zig");
 
 pub const LockdownIndex = struct {
     pub inline fn get() u3 {
         return asm volatile ("MRC p15, 5, %[result], c15, c4, 2"
             : [result] "=r" (-> u3),
         );
     }
 
     pub inline fn set(index: u3) void {
         return asm volatile ("MCR p15, 5, %[value], c15, c4, 2"
             :
             : [value] "r" (index),
         );
     }
 };
 
 pub const LockdownVA = packed struct(u32) {
     pub const Scope = enum(u1) {
         ApplicationSpecific = 0,
         Global = 1,
     };
 
     // address space ID
     asid: u8,
     _reserved_8: u1,
     scope: Scope,
     _reserved_10_11: u2,
     virtual_address: u20,
 
     pub inline fn get() @This() {
         return asm volatile ("MRC p15, 5, %[result], c15, c5, 2"
             : [result] "=r" (-> @This()),
         );
     }
 
     pub inline fn set(va: *const @This()) void {
         return asm volatile ("MCR p15, 5, %[value], c15, c5, 2"
             :
             : [value] "r" (@as(u32, @bitCast(va.*))),
         );
     }
 };
 
 pub const AccessPermissions = enum(u2) {
     TotalNoAccess = 0b00,
     UserNoAccess = 0b01,
     UserRead = 0b10,
     UserReadWrite = 0b11,
 };
 
 pub const AccessPermissionsExtended = enum(u1) {
     SupervisorRW = 0,
     SupervisorRO = 1,
 };
 
 pub const LockdownPA = packed struct(u32) {
     pub const Size = enum(u2) {
         @"16MB" = 0b00,
         @"4KB" = 0b01,
         @"64KB" = 0b10,
         @"1MB" = 0b11,
     };
     pub const Security = enum(u1) {
         Secure = 0,
         NonSecure = 1,
     };
 
     valid: bool,
     ap0: AccessPermissions,
     apx: AccessPermissionsExtended,
     _reversed_5_4: u2,
     size: Size,
     nstid: Security,
     nsa: Security,
     _reserved_11_10: u2,
     physical_address: u20,
 
     pub inline fn get() @This() {
         return asm volatile ("MRC p15, 5, %[result], c15, c6, 2"
             : [result] "=r" (-> @This()),
         );
     }
 
     pub inline fn set(pa: *const @This()) void {
         return asm volatile ("MCR p15, 5, %[value], c15, c6, 2"
             :
             : [value] "r" (@as(u32, @bitCast(pa.*))),
         );
     }
 };
 
 pub const LockdownAttributesRegister = packed struct(u32) {
     pub const PageTableEncodingPreset = enum(u5) {
         StronglyOrdered = 0b000_0_0,
         SharedDevice = 0b000_0_1,
         OuterInnerWriteThrough = 0b000_1_0,
         OuterInnerWriteBackNoAllocOnWrite = 0b000_1_1,
         OuterInnerNoncacheable = 0b001_0_0,
         OuterInnerWriteBackAllocOnWrite = 0b001_1_1,
         NonSharedDevice = 0b010_0_0,
     };
 
     pub const PageTableEncodingCached = packed struct(u5) {
         pub const CachePolicy = enum(u2) {
             Noncacheable = 0b00,
             WriteBackCachedWriteAlloc = 0b01,
             WriteThroughCachedNoWriteAlloc = 0b10,
             WriteBackCachedNoWriteAlloc = 0b11,
         };
 
         always_one: u1 = 1,
         outer_policy: CachePolicy,
         inner_policy: CachePolicy,
     };
 
     pub const PageTableEncodingManual = packed struct(u5) {
         b: u1,
         c: u1,
         tex: u3,
     };
 
     pub const PageTableEncoding = packed union {
         preset: PageTableEncodingPreset,
         cached: PageTableEncodingCached,
         manual: PageTableEncodingManual,
     };
 
     shared: bool,
     page_table_encoding: PageTableEncoding,
     execute_never: bool,
     domain: u4,
     _reserved_24_11: u14 = 0,
     subpages_valid: bool,
     ap1: AccessPermissions,
     ap2: AccessPermissions,
     ap3: AccessPermissions,
 
     pub inline fn get() @This() {
         return asm volatile ("MRC p15, 5, %[result], c15, c7, 2"
             : [result] "=r" (-> @This()),
         );
     }
 
     pub inline fn set(attr: *const @This()) void {
         return asm volatile ("MCR p15, 5, %[value], c15, c7, 2"
             :
             : [value] "r" (@as(u32, @bitCast(attr.*))),
         );
     }
 };
 
 pub const DomainAccessControlRegister = packed struct(u32) {
     pub const DomainAccess = enum(u2) {
         NoAccess = 0b00,
         Client = 0b01,
         Manager = 0b11,
     };
 
     // Inconvenient but necessary to ensure ordering
     d0: DomainAccess = .NoAccess,
     d1: DomainAccess = .NoAccess,
     d2: DomainAccess = .NoAccess,
     d3: DomainAccess = .NoAccess,
     d4: DomainAccess = .NoAccess,
     d5: DomainAccess = .NoAccess,
     d6: DomainAccess = .NoAccess,
     d7: DomainAccess = .NoAccess,
     d8: DomainAccess = .NoAccess,
     d9: DomainAccess = .NoAccess,
     d10: DomainAccess = .NoAccess,
     d11: DomainAccess = .NoAccess,
     d12: DomainAccess = .NoAccess,
     d13: DomainAccess = .NoAccess,
     d14: DomainAccess = .NoAccess,
     d15: DomainAccess = .NoAccess,
 
     pub inline fn get() @This() {
         return asm volatile ("MRC p15, 0, %[result], c3, c0, 0"
             : [result] "=r" (-> @This()),
         );
     }
 
     pub inline fn set(domains: *const @This()) void {
         return asm volatile ("MCR p15, 0, %[value], c3, c0, 0"
             :
             : [value] "r" (@as(u32, @bitCast(domains.*))),
         );
     }
 
     pub inline fn set_all(access: DomainAccess) void {
         const domains: @This() = .{
             .d0 = access,
             .d1 = access,
             .d2 = access,
             .d3 = access,
             .d4 = access,
             .d5 = access,
             .d6 = access,
             .d7 = access,
             .d8 = access,
             .d9 = access,
             .d10 = access,
             .d11 = access,
             .d12 = access,
             .d13 = access,
             .d14 = access,
             .d15 = access,
         };
 
         domains.set();
         mem.barrier(.Instruction);
     }
 };
 
 pub const TLBTypeRegister = packed struct(u32) {
     unified: bool,
     _reserved_7_1: u7,
     data_lockable_size: u8,
     instruction_lockable_size: u8,
     _reserved_31_24: u8,
 
     pub inline fn get() @This() {
         return asm volatile ("MRC p15, 0, %[result], c0, c0, 3"
             : [result] "=r" (-> @This()),
         );
     }
 
     pub inline fn set(domains: *const @This()) void {
         return asm volatile ("MCR p15, 0, %[value], c0, c0, 3"
             :
             : [value] "r" (@as(u32, @bitCast(domains.*))),
         );
     }
 };
 
 pub const OuterCacheableAttr = enum(u2) {
     OuterNoncacheable = 0b00,
     WriteBackWriteAlloc = 0b01,
     WriteThrough = 0b10,
     WriteBackNoWriteAlloc = 0b11,
 };
 
 pub const InnerCacheableAttr = enum(u3) {
     Noncacheable = 0b000,
     StronglyOrdered = 0b001,
     Device = 0b011,
     InnerWriteThrough = 0b110,
     InnerWriteBack = 0b111,
 };
 
 pub const TranslationTableBaseRegister0 = packed struct(u32) {
     inner_cacheable: bool = false,
     shared: bool = false,
     ecc: bool = false,
     outer_cacheable_attr: OuterCacheableAttr = .OuterNoncacheable,
     translation_table_base: u27,
 
     pub inline fn get() @This() {
         return asm volatile ("MRC p15, 0, %[result], c2, c0, 0"
             : [result] "=r" (-> @This()),
         );
     }
 
     pub inline fn set(ttbc: *const @This()) void {
         return asm volatile ("MCR p15, 0, %[value], c2, c0, 0"
             :
             : [value] "r" (@as(u32, @bitCast(ttbc.*))),
         );
     }
 };
 
 pub const TranslationTableBaseRegister1 = packed struct(u32) {
     inner_cacheable: bool,
     shared: bool,
     ecc: bool,
     outer_cacheable_attr: OuterCacheableAttr,
     // _reserved_13_5: u9,
     translation_table_base: u27,
 
     pub inline fn get() @This() {
         return asm volatile ("MRC p15, 0, %[result], c2, c0, 1"
             : [result] "=r" (-> @This()),
         );
     }
 
     pub inline fn clear() void {
         const zero: @This() = @bitCast(@as(u32, 0));
         zero.set();
     }
 
     pub inline fn set(ttbc: *const @This()) void {
         return asm volatile ("MCR p15, 0, %[value], c2, c0, 1"
             :
             : [value] "r" (@as(u32, @bitCast(ttbc.*))),
         );
     }
 };
 
 // ARM ARM only defines boundary_size
 // ARM1176JZF-S specifies more on top
 pub const TranslationTableBaseControl = packed struct(u32) {
     pub const BoundarySize = enum(u3) {
         @"16KB" = 0b000,
         @"8KB" = 0b001,
         @"4KB" = 0b010,
         @"2KB" = 0b011,
         @"1KB" = 0b100,
         @"512B" = 0b101,
         @"256B" = 0b110,
         @"128B" = 0b111,
     };
 
     boundary_size: BoundarySize = .@"16KB",
     _reserved_3: u1 = 0,
     page_table_walk_0: u1 = 0,
     page_table_walk_1: u1 = 0,
     _reserved_31_6: u26 = 0,
 
     pub inline fn get() @This() {
         return asm volatile ("MRC p15, 0, %[result], c2, c0, 2"
             : [result] "=r" (-> @This()),
         );
     }
 
     pub inline fn set(ttbc: *const @This()) void {
         return asm volatile ("MCR p15, 0, %[value], c2, c0, 2"
             :
             : [value] "r" (@as(u32, @bitCast(ttbc.*))),
         );
     }
 };
 
 pub const ContextId = packed struct(u32) {
     asid: u8 = 0,
     pid: u24 = 0,
 
     pub inline fn get() @This() {
         return asm volatile ("MRC p15, 0, %[result], c13, c0, 1"
             : [result] "=r" (-> @This()),
         );
     }
 
     pub inline fn set(ctx: *const @This()) void {
         return asm volatile ("MCR p15, 0, %[value], c13, c0, 1"
             :
             : [value] "r" (@as(u32, @bitCast(ctx.*))),
         );
     }
 
     pub inline fn clear() void {
         const ctx: ContextId = .{};
         ctx.set();
     }
 };
 
 pub const FirstLevelDescriptor = packed struct(u32) {
     pub const Fault = packed struct(u30) {
         _ignore_31_2: u30 = 0,
     };
     pub const Coarse = packed struct(u30) {
         _reserved_0: u1 = 0,
         not_secure: bool = false,
         _reserved_1: u1 = 0,
         domain: u4,
         ecc: bool = false,
         coarse_base_address: u22,
     };
     pub const Section = packed struct(u30) {
         b: u1,
         c: u1,
         never_execute: bool,
         domain: u4,
         ecc: bool = false,
         ap: AccessPermissions,
         tex: u3,
         apx: AccessPermissionsExtended,
         shared: bool,
         not_global: bool,
         is_supersection: bool = false,
         not_secure: bool = false,
         section_base_address: u12,
     };
     pub const SuperSection = packed struct(u30) {
         b: u1,
         c: u1,
         never_execute: bool,
         base_address_39_36: u4,
         ecc: bool = false,
         ap: AccessPermissions,
         tex: u3,
         apx: AccessPermissionsExtended,
         shared: bool,
         not_global: bool,
         is_supersection: bool = true,
         not_secure: bool = false,
         base_address_35_32: u4,
         section_base_address: u8,
     };
 
     pub const Type = enum(u2) {
         Fault = 0b00,
         CoarsePageTable = 0b01,
         Section = 0b10,
     };
 
     ty: Type,
     descriptor: packed union {
         fault: Fault,
         coarse: Coarse,
         section: Section,
         supersection: SuperSection,
     },
 };
 
 pub const SecondLevelDescriptor = packed struct(u32) {
     pub const Fault = packed struct(u30) {
         _ignore_31_2: u30 = 0,
     };
     pub const LargePage = packed struct(u30) {
         b: u1,
         c: u1,
         ap: AccessPermissions,
         _reserved_8_6: u3 = 0,
         apx: AccessPermissionsExtended,
         shared: bool,
         not_global: bool,
         tex: u3,
         never_execute: bool,
         base_address: u16,
     };
     pub const SmallPage = packed struct(u30) {
         b: u1,
         c: u1,
         ap: AccessPermissions,
         tex: u3,
         apx: AccessPermissionsExtended,
         shared: bool,
         not_global: bool,
         base_address: u20,
     };
 
     pub const Type = enum(u2) {
         Fault = 0b00,
         LargePage = 0b01,
         SmallPageNeverExecute = 0b11,
         SmallPageExecutable = 0b10,
     };
     ty: Type,
     descriptor: packed union {
         fault: Fault,
         large_page: LargePage,
         small_page: SmallPage,
     },
 };
 
 pub const TranslationMode = enum {
     PrivilegedRead,
     PrivilegedWrite,
     UserRead,
     UserWrite,
 };
 
 pub const TranslationResult = packed struct(u32) {
     pub const TranslationSuccess = packed struct(u31) {
         _reserved_1: u1,
         outer: OuterCacheableAttr,
         inner: InnerCacheableAttr,
         shared: bool,
         _unused_8: u1,
         not_secure: bool,
         address: u22,
     };
     pub const TranslationAborted = packed struct(u31) {
         fsr_bits: u6,
         _reserved_7_31: u25,
     };
 
     aborted: bool,
     inner: packed union {
         success: TranslationSuccess,
         aborted: TranslationAborted,
     },
 };
 
 // 3-82
 // Write to p15, c7, c4, 0 with VA and read to get PA + extra
 pub inline fn va_translation_cw(va: u32, comptime mode: TranslationMode) TranslationResult {
     const mode_asm = switch (mode) {
         .PrivilegedRead => "0",
         .PrivilegedWrite => "1",
         .UserRead => "2",
         .UserWrite => "3",
     };
 
     asm volatile ("MCR p15, 0, %[value], c7, c8, " ++ mode_asm
         :
         : [value] "r" (va),
     );
 
     return asm volatile ("MRC p15, 0, %[result], c7, c4, 0"
         : [result] "=r" (-> TranslationResult),
     );
 }
 
 pub fn init() void {
     // Reset MMU
     reset();
 
     // Read-Modify-Write XP in CP1
     // Ensure MMU is disabled
     var reg = system.SystemControlRegister.get();
     reg.extended_page_tables = true;
     reg.mmu_enabled = false;
     reg.set();
 }
 
 // We want to ensure the processor is in a known state, so:
 // 1. Invalidate all caches
 // 2. B2 (memory) ordering operations
 pub fn reset() void {
     // Instruction Cache/Data Cache
     system.invalidate_all_caches();
     // ITLB/DTLB
     system.invalidate_TLB();
 
     // B2 ordering
     // Ensure maintenance completes
     mem.barrier(.Write);
 
     // // Flush BTB as part of reset
     // system.flush_btb();
 
     // // Ensure completion
     // mem.barrier(.Write);
     // // Required after BTB flush
     // mem.barrier(.Instruction);
 }
 
 // 6-9: 6.4.1 - Enabling the MMU
 // 1. Program all relevant CP15 registers
 // 2. Program first-level and second-level page tables as required
 // 3. Disable and invalidate instruction cache
 // 4. Enable MMU by setting bit 0 in System Control Register
 // 5. Optionally reenable instruction cache
 pub noinline fn enable() void {
     // 1. Program all relevant CP15 registers
     // Should be done by reset/user
 
     // 2. Program first-level and second-level page tables
     // Should be done by user (via set_context_ttbr0)
 
     // 3. Disable instruction cache
     var reg = system.SystemControlRegister.get();
     reg.level_one_instruction_cache = false;
     reg.set();
 
     // 3. Invalidate instruction cache
     mem.barrier(.Instruction);
     system.invalidate_icache();
     // Ensure completion of instruction cache maintenance
     mem.barrier(.Write);
 
     // 4. Enable MMU
     reg.mmu_enabled = true;
     reg.set();
 
     // Ensure completion of enabling
     mem.barrier(.Instruction);
 
     // Required after enabling MMU
     system.flush_btb();
     // Required after BTB flush
     mem.barrier(.Instruction);
 }
 
 // 6-9: 6.4.2 - Disabling the MMU
 // 1. Clear bit 2 to 0 in System Control Register (level one data cache)
 // 2. Clear bit 0 to 0 in System Control Register (MMU Enabled)
 pub noinline fn disable() void {
     // 0. Clear cache so entries are properly written
     system.clear_entire_data_cache();
     mem.barrier(.Write);
 
     var reg = system.SystemControlRegister.get();
 
     // 1. Clear bit 2 to 0
     reg.level_one_data_cache = false;
     reg.set();
 
     mem.barrier(.Instruction);
 
     // Invalidate instruction cache
     system.invalidate_icache();
     mem.barrier(.Write);
 
     // 2. Clear bit 0 to 0
     reg.mmu_enabled = false;
     reg.set();
 
     mem.barrier(.Instruction);
 
     // BTB is to be flushed after any change to MMU
     system.flush_btb();
     // Prefetch flush is required after BTB flush
     mem.barrier(.Instruction);
 }
 
 // 3-129
 pub fn set_context(ctx: ContextId) void {
     // "You must ensure that software performs a Data Synchronization
     // Barrier operation before changes to this register."
     mem.barrier(.Write);
 
     ctx.set();
 
     // "You must execute an IMB instruction immediately after changes
     // to the Context ID Register."
     system.flush_btb();
     mem.barrier(.Instruction);
 }
 
 // B2-25 Synchronization of Changes of ASID and TTBR
 // 1. Change ASID to 0
 // 2. Prefetch Flush
 // 3. Change TTRB
 // 4. Prefetch Flush
 // 5. Change ASID to new value
 pub fn set_context_ttbr0(ctx: ContextId, ttrb0: TranslationTableBaseRegister0) void {
     mem.barrier(.Write);
 
     // 1. Change ASID to 0
     const cleared: ContextId = .{};
     cleared.set();
     mem.barrier(.Instruction);
 
     // 3. Set control N = 0 to use TTRB0
     const control: TranslationTableBaseControl = .{
         // Specifies TTRB0 (3-62), N = 0
         .boundary_size = .@"16KB",
     };
     control.set();
 
     // 3. Set TTRB0
     ttrb0.set();
 
     // 4. Prefetch flush
     mem.barrier(.Instruction);
 
     // 5. Change ASID to new value
     ctx.set();
 
     // BTB flush required after change to ContextID
     system.flush_btb();
     mem.barrier(.Instruction);
 }
 
 // B2.7.3
 // Synchronize PTE modifications
 //
 // 1. Store PTE
 // 2. Clean PTE line
 // 3. DSB
 // 4. Invalidate TLB
 // 5. Invalidate BTB
 // 6. DSB
 // 7. Prefetch
 pub fn sync_pte() void {
     // 1. Store page table
     // Should be done by user
 
     // 2. Clean page table
     // This ensures that the page table is fully committed to memory
     system.clear_entire_data_cache();
 
     // 3. DSB
     mem.barrier(.Write);
 
     // 4. Invalidate TLB
     system.invalidate_TLB();
 
     // 5. Invalidate BTB
     system.flush_btb();
 
     // 6. DSB
     mem.barrier(.Write);
 
     // 7. Prefetch
     mem.barrier(.Instruction);
 }
 
 pub fn set_domain(domain: DomainAccessControlRegister) void {
     domain.set();
     mem.barrier(.Instruction);
 }
 
 // Higher Level Abstractions
 
 pub fn is_enabled() bool {
     return system.SystemControlRegister.get().mmu_enabled;
 }