sylveos

debug.zig (5108B)

---

 const pi = @import("pi");
 
 const interrupts = pi.interrupts;
 const debug = pi.debug;
 const uart = pi.devices.mini_uart;
 const faults = pi.faults;
 const switching = pi.switching;
 
 var scheduler_registers: interrupts.Registers = undefined;
 var last_registers: interrupts.Registers = undefined;
 var count: usize = 0;
 
 fn dump_registers(regs: *const interrupts.Registers) void {
     uart.writer.print("Registers\n", .{}) catch {};
     for (regs.gp, 0..) |r, i| {
         uart.writer.print("  r{d} = 0x{X}\n", .{ i, r }) catch {};
     }
     uart.writer.print("  sp = 0x{X}\n  lr = 0x{X}\n  pc = 0x{X}\n", .{ regs.sp, regs.lr, regs.pc }) catch {};
     uart.writer.print("  psr = {s}\n", .{@tagName(regs.psr.mode)}) catch {};
     uart.flush();
 }
 
 fn single_step_handler(regs: interrupts.Registers) void {
     count += 1;
 
     uart.writer.print("fault: 0x{X} @ 0x{X}: {d}\n", .{ pi.mem.get_u32(@ptrFromInt(regs.pc)), regs.pc, count }) catch {};
     dump_registers(&regs);
     uart.flush();
 
     debug.set_breakpoint(0, regs.pc, .IMVAMismatch);
     uart.flush();
 
     // My guess why this is necessary is since regs lives in the stack
     // That will cause an explosion when the stack is switched
     last_registers = regs;
     switching.restore_state_user(&last_registers);
 }
 
 fn watchpoint_handler(regs: interrupts.Registers) void {
     count += 1;
 
     uart.writer.print("fault: 0x{X} @ 0x{X}: {d}\n", .{ pi.mem.get_u32(@ptrFromInt(regs.pc)), regs.pc, count }) catch {};
     uart.writer.print("  -> accessed address 0x{X}\n", .{debug.WCR.get_address(0)}) catch {};
     uart.flush();
 
     last_registers = regs;
     switching.restore_state(&last_registers);
 }
 
 fn syscall_handler(regs: interrupts.Registers) void {
     uart.writer.print("got syscall at level {s} @ 0x{X}!\n", .{ @tagName(regs.psr.mode), regs.pc }) catch {};
     uart.writer.print(" -> restoring to 0x{X}\n", .{regs.pc}) catch {};
 
     const sys = regs.gp[0];
     const arg0 = regs.gp[1];
 
     switch (sys) {
         1 => {
             uart.write_slice("exiting process\n");
             uart.flush();
 
             switching.restore_state(&scheduler_registers);
         },
         2 => {
             uart.write_byte(@truncate(arg0));
         },
         else => {
             uart.write_slice("illegal syscall\n");
         },
     }
 
     switching.restore_state(&regs);
 }
 
 fn count_registers() callconv(.naked) void {
     asm volatile (
         \\ mov r0, 0
         \\ mov r1, 1
         \\ mov r2, 2
         \\ mov r3, 3
         \\ mov r4, 4
         \\ mov r5, 5
         \\ mov r6, 6
         \\ mov r7, 7
         \\ mov r8, 8
         \\ mov r9, 9
         \\ mov r10, 10
         \\ mov r11, 11
         \\ mov r12, 12
         \\ mov r0, 1
         \\ bx lr
     );
 }
 
 // do null pointer bs
 fn watchpoint_test() callconv(.naked) void {
     asm volatile (
         \\ mov r0, #8
         \\ ldr r0, [r0]
         \\ str r0, [r0]
         \\ bx lr
     );
 }
 
 fn exit_trampoline() callconv(.naked) void {
     asm volatile (
         \\ mov r1, r0
         \\ mov r0, 1
         \\ swi 1
     );
 }
 
 pub fn main() !void {
     interrupts.disable_interrupts();
     uart.set_tx_interrupts(false);
 
     const didr = debug.DIDR.get();
     try uart.writer.print("Debug ID\n", .{});
     try uart.writer.print("  revision = {d}\n  variant = {d}\n  debug revision = {d}\n  debug version = {d}\n", .{
         didr.revision,
         didr.variant,
         didr.debug_revision,
         didr.debug_version,
     });
     try uart.writer.print("  breakpoints = {d}\n  watchpoints = {d}\n", .{ didr.breakpoint_pairs + 1, didr.watchpoint_pairs + 1 });
 
     interrupts.set_exception_handler(.PrefetchAbort, single_step_handler);
     interrupts.set_exception_handler(.DataAbort, watchpoint_handler);
     interrupts.set_exception_handler(.SoftwareInterrupt, syscall_handler);
     try uart.writer.print("Set exception handlers\n", .{});
 
     try uart.writer.print("Running as {s}\n", .{@tagName(pi.PSR.get_c().mode)});
     debug.enable_monitor_mode();
     try uart.writer.print("Enabled monitor mode\n", .{});
 
     debug.set_breakpoint(0, 0, .IMVAMismatch);
     try uart.writer.print("Set breakpoint\n", .{});
 
     var psr = pi.PSR.get_c();
     psr.mode = .User;
 
     var new_registers: interrupts.Registers = .{
         .gp = .{0} ** 13,
         .pc = @intFromPtr(&count_registers),
         .sp = 0,
         .lr = @intFromPtr(&exit_trampoline),
         .psr = psr,
     };
     dump_registers(&new_registers);
 
     try uart.writer.print("Testing stepping\n", .{});
     switching.switch_state(&scheduler_registers, &new_registers);
     try uart.writer.print("Stepping success\n", .{});
 
     try uart.writer.print("Testing watchpoint\n", .{});
     new_registers = .{
         .gp = .{0} ** 13,
         .pc = @intFromPtr(&watchpoint_test),
         .sp = 0,
         .lr = @intFromPtr(&exit_trampoline),
         .psr = psr,
     };
     debug.clear_breakpoint(0);
     debug.set_watchpoint(0, 0x8, .Either);
     count = 0;
     switching.switch_state(&scheduler_registers, &new_registers);
     try uart.writer.print("Watchpoint success\n", .{});
 
     debug.disable_monitor_mode();
 
     while (true) {}
 }