sylveos

commit fa0aa92896c22f40ce2c3539343a662a2d76aabb
parent 48f2b74cecdc028db2cdb7003bf74abcba87c887
Author: Sylvia Ivory <git@sivory.net>
Date:   Tue, 13 Jan 2026 19:53:19 -0800

Add memory barrier

Diffstat:
A
src/barrier.zig
 | 
19
+++++++++++++++++++

1 file changed, 19 insertions(+), 0 deletions(-)
diff --git a/src/barrier.zig b/src/barrier.zig
@@ -0,0 +1,19 @@
+// https://developer.arm.com/documentation/ddi0333/h/system-control-coprocessor/system-control-processor-registers/c7--cache-operations
+
+released: bool,
+
+pub fn obtain() @This() {
+    asm volatile ("MCR p15, 0, r0, c7, c10, 4");
+
+    return .{ .released = false };
+}
+
+pub fn release(barrier: *@This()) void {
+    if (barrier.released) @panic("attempt to release already released barrier");
+    barrier.released = true;
+    asm volatile ("MCR p15, 0, r0, c7, c10, 5");
+}
+
+pub fn active(barrier: *@This()) void {
+    return !barrier.released;
+}